ABOUT PACMAN

Who is Pacman?

Name :- Paul Antony Collins (aka PAC or PACMAN due to registering scores on video games)
Date of Birth  :- 1st October, 1963
Marital Status :- Single

Photo

Sorry if this breaks your screen but this is me :-

Where I Live

I live in a village called Histon, just north of the famous University City of Cambridge, UK.

Where I'm From

I originate from Scunthorpe, North Lincolnshire in the North of England near the border of South Yorkshire.

Where I Work

I'm currently working as a Senior Electronics Design Engineer for a relatively small company called Arcom Control Systems Ltd. They design embedded boards, single board computers and associated peripherals and have been in buisness since 1982.

I last worked for a relatively small company called Radiant Networks PLC as a Hardware Engineer in their Network Systems Group. They're developing a unique way of delivering "broadband" data services to small businesses and residential customers and have been in business since 1997.

Prior to my Radiant I worked for a large multi-national telecomms company called Marconi. I thought I had job security with them but after 15 years in hardware design they saw fit to close the Poole site with the loss of 600 R&D people.

My CV:

Paul Collins

Profile:

A self motivated Electronics Engineer with 17 years experience

Key Skills:

• Experienced in all stages of the product cycle from concept through to installation and support
• Experience of setting up and contributing to ISO9000 based development processes
• High-speed digital design including signal integrity analysis (HyperLynx BoardSim) and timing considerations (Chronology Timing Designer)
• Microprocessor design using Motorola (68K, PowerQUICC) and Virata (Helium with dual ARM7 cores) products
• FPGA/CPLD design – Altera (Max+PLUS II – schematics and AHDL), Mentor FPGA Advantage (Renoir/ModelSim/Leonardo Spectrum – VHDL) and Lattice ispLEVER (ABEL and VHDL)
• Implementing Boundary Scan (JTAG) to improve product testability using Asset InterTech and Corelis ScanPlus
• Schematic capture and PCB layout using Zuken-Redac (Visula and Cadstar), Mentor (BoardStation) and Viewlogic (ViewDraw)
• Awareness of C/Assembler programming and analogue interfacing
• Capable of adapting to any design environment with the ability to work as an individual or as a member of a multi-disciplined team

Additional Skills:

• Hardware design tools specification, selection, installation and support
• Windows 9x/NT/ME/XP – fully proficient and very knowledgeable
• Prototype SMT and TH PCB assembly and rework
• PC building – specification, build, configuration and support
• Web-site design using MS FrontPage 2000
• MS Office 2000 and Visio

Achievements:

• Individual contribution award for place and route of a Motorola PowerQUICC microprocessor daughterboard. Initial efforts from an in-house CAD bureau were not acceptable. With CAD resources limited and being self-taught I was tasked with the rework. The final PCB was 2 inches smaller and used 2 fewer routing layers
• Individual contribution award for helping complete the design of a daughterboard replacing an ASIC ahead of a tight schedule
• Grant of a patent for producing a design that out-performed available off the shelf solutions available at the time. An existing E1 (2Mbit/s) standard circuit used on high-volume products had to be manually tuned during production and the components used were due for obsolescence. The completed design resulted in both improved performance and a cost saving

Education:

1982 – 1986: BSc Electronic Systems & Control Engineering – Sheffield City Polytechnic
1980 – 1982: TEC Diploma in Technology – North Lindsey College of Technology

Career History:

2001 – 2003: Radiant Networks PLC, Little Chesterford, Essex 

Radiant are a small company producing an innovative Broadband Fixed Wireless Access system. I was part of a small design team developing the company’s digital products working on the following projects: 

2003:

• Design of an 8-port E1 (2Mbit/s) and T1 (1.544Mbit/s) IMA daughterboard

2002:

• Specification of an E3 (34Mbit/s) and T3 (45Mbit/s) line interface daughterboard
• Redesign of a Virata Helium 210 processor board to support both 66MHz and 80MHz versions of the processor (based upon a dual ARM7 core). This involved catering for EMC compliance (original failed compliance tests), timing differences, new features and cost reduction. The design incorporated VLSI in the form of Lattice CPLDs, SDRAM, Flash and an ATM25 PHY and included 10Base-T, ATM25, USB and RS232 ports
• Design of a 6-port ATM25 daughterboard

2001:

• Fault finding, EMC testing and subsequent rework of a 4-port E1/T1 daughterboard
• Design of a 19” sub-rack to house double-height extended Eurocard PCBs including a rear-panel interface board and passive backplane

1986 – 2001: Marconi PLC, Poole, Dorset

Marconi is large company producing optical and digital switches, multiplexers and cross-connects for the Telecomms market. I was part of a medium sized design team developing primarily ATM switching products working on the following projects:

2001:

• Design tools specification, procurement, installation and support

2000:

• Redesign of an ATM unit for SDH to incorporate E3, T3 and STM-1 (155Mbit/s – electrical and optical) interfaces. Customer premises unit based upon a Motorola PowerQUICC processor with VLSI including Flash, SDRAM, SRAM, CPLDs (Altera MAX7000) and ATM switching devices

1998:

• Design of an ATM card for the company’s SMA range of SDH multiplexers. Part of a 2 man team and responsible for the integration of the VLSI devices, glue logic, CPLDs (Altera MAX7000), placement and partial routing
• Placement and routing of Motorola PowerQUICC microprocessor daughterboard based around the IEEE P1386.1 PMC (PCI Mezzanine Card) standard incorporating Flash, SDRAM, SRAM and PCI master VLSI devices

1997:

• Design of an STM-1 line interface unit
• Design of a 10Base-T Ethernet PCM module based upon an AMD PHY

Pre-1997:

• Seconded to another Marconi site to provide FPGA support
• Design of a daughterboard to replace a SONET ASIC
• Design of a replacement E1 standard circuit
• Sub-system proving and fault support for System X digital switch products

Training:

ATM, SDH, Telecomms/Datacomms, Boundary Scan, FPGA Advantage, Doulos Comprehensive VHDL, MS Office, C

Interests:

• PC building, upgrading, maintenance and support
• Keen golfer – 10 handicap
• Web-site design and maintenance – author of the world leading web-site for PC start-up programs, respected by Tech Support staff worldwide